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PS8093E 05/23/06
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PI74ALVCH162601
18-Bit Universal Bus Transceiver
with 3-State Outputs
Logic Block Diagram
Product Features
Designed for low voltage operation, VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
ProductDescription
The PI74ALVCH162601 uses D-type latches and D-type flip-flops
with 3-state outputs to allow data flow in transparent, latched, and
clocked modes.
Data flow in each direction is controlled by Output Enable (OEAB
andOEBA),LatchedEnable(LEABandLEBA),andClock(CLKAB
andCLKBA)inputs.TheclockcanbecontrolledbytheClockEnable
(CLKENABandCLKENBA)inputs. ForA-to-Bdataflow,thedevice
operates in the transparent mode when LEAB is HIGH. When LEAB
is LOW, the A data is latched if CLKAB is held at a high or low logic
level. If LEAB is low, the A-bus is stored in the latch/flip-flop on the
low-to-high transition of CLKAB. When OEAB is low, the outputs
are active. When OEAB is HIGH, the outputs are in the high-
impedance state.
DataflowforBtoAissimilartothatofAtoBbutusesOEBA,LEBA,
CLKBA,andCLKENBA.
To reduce overshoot and undershoot, the B-port outputs include
26
Ω series resistors.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH162601 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
06-0134